Atmel公司的ATR0621PGPS基带处理器包括有16通路的GPS相关器和基于ARM7TDMI的处理器核.ATR0621P具有高性能的32位RISC架构和非常低的功耗.此外,它还有两个USART和一个USB端口.ATR0621P的接收灵敏度为-140dBm,跟踪灵敏度为-150dBm.本文介绍了ATR0621P的主要特性,方框图以及多种应用连接图如ATR0621P外部连接图,外接闪存连接图,串行EEPROM连接图以及采用内部LDO和备份电源的连接图和采用内部LDO,USB电源和备份电源的连接图.TheGPSbaseb

Atmel公司的ATR0621PGPS基带处理器包括有16通路的GPS相关器和基于ARM7TDMI的处理器核. ATR0621P具有高性能的32位RISC架构和非常低的功耗.此外,它还有两个USART和一个USB端口. ATR0621P的接收灵敏度为-140dBm,跟踪灵敏度为-150dBm.本文介绍了ATR0621P的主要特性,方框图以及多种应用连接图如ATR0621P外部连接图, 外接闪存连接图, 串行EEPROM连接图以及采用内部LDO和备份电源的连接图和采用内部LDO,USB电源和备份电源的连接图.

The GPS baseband processor ATR0621P includes a 16-channel GPS correlator and is basedonthe ARM7TDMI processor core.

This processor has a high-performance 32-bit RISC architecture and very low power consumption. In addition, a large number of internally bankedregisters result in very fast exception handling, making the device ideal for real-time control applications. The ATR0621P has two USART and an USB device port. This port is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. The ATR0621P has a direct connection to off-chip memory, including Flash, through the External Bus Interface (EBI).

The ATR0621P includes full GPS firmware, licensed from u-blox AG, which performs the basic GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for off-chip Flash memory or ROM.

The firmware supports e.g. the NMEA® protocol (2.1 and 2.3), a binary protocol for PVT data, configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS) and A-GPS (aiding). It is also possible to store the configurationsettings in an optional external EEPROM.

The ATR0621P is manufactured using the Atmel® high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator and a wide range of peripheral functions on a monolithic chip, the ATR0621P provides a highly-flexible and cost-effective solution for GPS applications.

The ATR0621P architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA" Bridge provides an interface between the ASB and the APB.

An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPIand the on-chip and off-chip memories without processor intervention. Most importantly, the PDC2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced.

The ATR0621P peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address space.) The peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status, and interrupt registers.

To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits, and the third address reads the value stored in the register. A bit can be set or reset by writing a “1” to the corresponding position at the appropriate address. Writing a “0” has no effect.

Individual bits can thus be modified without having to use costly read-modify-write and complex bit-manipulation instructions.